3.4.4.8 Program Data Flow in Cache Mode

The CPU program bus has access to both the ISB and the Instruction Cache during a program data fetch. Note that the program data will always be sourced in the order listed. There are these general cases that can occur during a fetch of a program data word:

• The required program data is available in the cache memory (cache hit)
• The required program data is available in one of the ISB buffers (cache miss, ISB hit)
• The required program data is not available in either the cache memory or the ISB buffers (cache miss, ISB miss)