3.4.4.10 Cache Busy Cycles

Each time program data is consumed by the CPU from the ISB that is not in the Instruction Cache, the program word will be written to the Instruction Cache on the following clock cycle. If the CPU also needs instruction data on the next clock cycle, the instruction data will be sourced from the ISB because the write to the Instruction Cache is in progress. This will result in a cache busy cycle due to the cache write.

On the clock cycle following a cache write, the ISB line will be invalidated because the program data are now stored in the Instruction Cache. This frees the ISB line for future prefetch activity.