3.4.4.2 SFR Interface for Module Operation
The PBU SFR interface provides control and status around the Cache and ISB; it also provides event signals to the CPU, such as memory integrity errors. The operation of the PBU is divided into three operating scenarios:
- Operation when the PBU is disabled (CHECON.ON = 0)
- Normal cache and ISB operation while the PBU is enabled (CHECON.ON = 1). This is the default mode of operation.
- Non-cacheable events that occur while the PBU is enabled
These operating scenarios are described in Module Operation When Cache Disabled, Module Operation When Cache Enabled and ISB Operations.