3.4.4.1 Overview

The cache provides an improved instruction rate to the CPU from Flash program memory. The cache increases the instruction rate in two ways. First, program data words are stored in a prefetch buffer. This allows the CPU to use program data from one buffer location while a fetch from Flash memory fills other buffer locations. Secondly, it increases the instruction rate by storing (caching) program data words previously fetched from the program memory for later use. Specifically, the instruction rate is improved because the fetch from the local cache memory takes less time than a fetch from the program memory.

The PBU responds to program data fetches from the CPU instruction bus and fetches the necessary program data from Flash memory. Fetches from the CPU data bus and data fetches from other bus masters are sourced through the data path and buffer in the Flash memory.

The cache requested 32-bit program data can come from multiple sources:

When Flash access time is fast and the Flash data word is large enough to contain multiple instructions, a prefetch buffer alone can suffice to support the CPU instruction rate without stall cycles. However, the Instruction Cache is particularly helpful during program flow changes. At these times, the prefetch buffer will not have the required program data, and a new fetch must be started at a new location. The Instruction Cache helps eliminate extra latency associated with Flash fetch at a new program flow location.