3.4.4.6 Cache Buffer
The Cache Buffer is internally configured to provide a variable size (at compile time) and 4-way set associative operation.
The Instruction Cache has memory elements to store these data:
- One 128-bit program memory data word per line, plus a parity bit for each word
- Address tag for each line of cache
- Valid bit for data word (128-bit) in each line
Parity calculation and error detection on a chosen cache line are shown in Figure 3-26.
For an Instruction Cache line to be valid, the valid bit must be set, and the even parity check must pass. If a bit error occurs in the cache memory causing a parity error, recovery is made by invalidating the cache line associated with the error. The cache line can simply be re-fetched from program memory, resulting in additional latency caused by the new fetch.
Figure 3-24 shows how program data are organized within the Instruction Cache line. The Tag address is based on the upper address of the program word, as depicted in Figure 3-25.
Each program word in the Instruction Cache line stores at least four instructions, as shown in Figure 3-24. The program word can store more than four instructions if some of the instructions are 16-bit instructions. If all instructions are 16-bit instructions, then the program word will contain eight instructions. In normal program instruction flow, the typical program word will contain a mix of 16 and 32-bit instructions.