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10.2.3 DMA Control Registers Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0ABC DMACON 15:8 DMAEN DMASIDL 7:0 PRSSEL 0x0ABE DMABUF 15:8 DMABUF[15:8] 7:0 DMABUF[7:0] 0x0AC0 DMAL 15:8 LADDR[15:8] 7:0 LADDR[7:0] 0x0AC2 DMAH 15:8 HADDR[15:8] 7:0 HADDR[7:0] 0x0AC4 DMACH0 15:8 Reserved NULLW RELOAD CHREQ 7:0 SAMODE[1:0] DAMODE[1:0] TRMODE[1:0] SIZE CHEN 0x0AC6 DMAINT0 15:8 DBUFWF CHSEL[6:0] 7:0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF HALFEN 0x0AC8 DMASRCn 15:8 SADDR[15:8] 7:0 SADDR[7:0] 0x0ACA DMADSTn 15:8 DADDR[15:8] 7:0 DADDR[7:0] 0x0ACC DMACNTn 15:8 CNT[15:8] 7:0 CNT[7:0] 0x0ACE DMACH1 15:8 Reserved NULLW RELOAD CHREQ 7:0 SAMODE[1:0] DAMODE[1:0] TRMODE[1:0] SIZE CHEN 0x0AD0 DMAINT1 15:8 DBUFWF CHSEL[6:0] 7:0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF HALFEN 0x0AD2 DMASRCn 15:8 SADDR[15:8] 7:0 SADDR[7:0] 0x0AD4 DMADSTn 15:8 DADDR[15:8] 7:0 DADDR[7:0] 0x0AD6 DMACNTn 15:8 CNT[15:8] 7:0 CNT[7:0] 0x0AD8 DMACH2 15:8 Reserved NULLW RELOAD CHREQ 7:0 SAMODE[1:0] DAMODE[1:0] TRMODE[1:0] SIZE CHEN 0x0ADA DMAINT2 15:8 DBUFWF CHSEL[6:0] 7:0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF HALFEN 0x0ADC DMASRCn 15:8 SADDR[15:8] 7:0 SADDR[7:0] 0x0ADE DMADSTn 15:8 DADDR[15:8] 7:0 DADDR[7:0] 0x0AE0 DMACNTn 15:8 CNT[15:8] 7:0 CNT[7:0] 0x0AE2 DMACH3 15:8 Reserved NULLW RELOAD CHREQ 7:0 SAMODE[1:0] DAMODE[1:0] TRMODE[1:0] SIZE CHEN 0x0AE4 DMAINT3 15:8 DBUFWF CHSEL[6:0] 7:0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF HALFEN 0x0AE6 DMASRCn 15:8 SADDR[15:8] 7:0 SADDR[7:0] 0x0AE8 DMADSTn 15:8 DADDR[15:8] 7:0 DADDR[7:0] 0x0AEA DMACNTn 15:8 CNT[15:8] 7:0 CNT[7:0]
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