5.6.1.1 Nonvolatile Memory (NVM) Control Register
- These bits can only be reset on a POR.
- If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay (TVREG) before Flash memory becomes operational.
- All other combinations of NVMOP[3:0] are unimplemented.
- Execution of the
PWRSAVinstruction is ignored while any of the NVM operations are in progress. - Two adjacent words on a 4-word boundary are programmed during execution of this operation.
Legend: C = Clearable bit; SO = Settable Only bit
| Name: | NVMCON |
| Offset: | 0x8D0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WR | WREN | WRERR | NVMSIDL | RPDF | URERR | ||||
| Access | R/SO | R/W | R/C | R/W | R/W | R/C | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NVMOP[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 15 – WR Write Control bit(1)
| Value | Description |
|---|---|
1 |
Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete. |
0 |
Program or erase operation is complete and inactive. |
Bit 14 – WREN Write Enable bit(1)
| Value | Description |
|---|---|
1 |
Enables Flash program/erase operations |
0 |
Inhibits Flash program/erase operations |
Bit 13 – WRERR Write Sequence Error Flag bit(1)
| Value | Description |
|---|---|
1 |
An improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the WR bit). |
0 |
The program or erase operation completed normally. |
Bit 12 – NVMSIDL NVM Stop in Idle Control bit(2)
| Value | Description |
|---|---|
1 |
Flash voltage regulator goes into Standby mode during Idle mode. |
0 |
Flash voltage regulator is active during Idle mode. |
Bit 9 – RPDF Row Programming Data Format bit
| Value | Description |
|---|---|
1 |
Row data to be stored in RAM are in a compressed format. |
0 |
Row data to be stored in RAM are in an uncompressed format. |
Bit 8 – URERR Row Programming Data Underrun Error bit
| Value | Description |
|---|---|
1 |
Indicates row programming operation has been terminated. |
0 |
No data underrun error is detected. |
Bits 3:0 – NVMOP[3:0] NVM Operation Select bits(1,3,4)
| Value | Description |
|---|---|
1111 |
Reserved |
1110 |
User memory bulk erase operation |
1101 |
Reserved |
1100 |
Reserved |
1011 |
Reserved |
1010 |
Reserved |
1001 |
Reserved |
1000 |
Reserved |
0111 |
Reserved |
0101 |
Reserved |
0100 |
Reserved |
0011 |
Memory page erase operation |
0010 |
Memory row program operation |
0001 |
Memory double-word operation(5) |
0000 |
Reserved |