8.1 Parallel I/O (PIO) Ports
All port pins have 12 registers directly associated with their operation
as digital I/Os. The Data Direction register (TRISx) determines whether the pin is an
input or an output. If the data direction bit is a ‘1’, then the pin is
an input.
All port pins are defined as inputs after a Reset.
| Pin | Function |
|---|---|
| Reads from the latch (LATx) | Read the latch |
| Writes to the latch | Write the latch |
| Reads from the port (PORTx) | Read the port pins |
| Writes to the port pins | Write the latch |
Any bit and its associated data and control registers that are not valid for a particular device are disabled. This means the corresponding LATx and TRISx registers, as well as the port pin, are read as zeros.
When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. Table 8-1 shows the pin availability. Figure 8-1 shows the 5V input tolerant pins across this device.
| Device | Rx15 | Rx14 | Rx13 | Rx12 | Rx11 | Rx10 | Rx9 | Rx8 | Rx7 | Rx6 | Rx5 | Rx4 | Rx3 | Rx2 | Rx1 | Rx0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PORTA | ||||||||||||||||
| dsPIC33CKXXXMC502/102 | — | — | — | — | — | — | — | — | — | — | — | X | X | X | X | X |
| dsPIC33CKXXXMC503/103 | — | — | — | — | — | — | — | — | — | — | — | X | X | X | X | X |
| dsPIC33CKXXXMC505/105 | — | — | — | — | — | — | — | — | — | — | — | X | X | X | X | X |
| dsPIC33CKXXXMC506/106 | — | — | — | — | — | — | — | — | — | — | — | X | X | X | X | X |
| ANSELA | — | — | — | — | — | — | — | — | — | — | — | X | X | X | X | X |
| PORTB | ||||||||||||||||
| dsPIC33CKXXXMC502/102 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| dsPIC33CKXXXMC503/103 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| dsPIC33CKXXXMC505/105 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| dsPIC33CKXXXMC506/106 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| ANSELB | — | — | — | — | — | — | X | X | X | — | — | X | X | X | X | X |
| PORTC | ||||||||||||||||
| dsPIC33CKXXXMC502/102 | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| dsPIC33CKXXXMC503/103 | — | — | — | — | — | — | — | — | — | — | X | X | X | X | X | X |
| dsPIC33CKXXXMC505/105 | — | — | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| dsPIC33CKXXXMC506/106 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| ANSELC | — | — | — | — | — | — | — | — | X | X | — | — | X | X | X | X |
| PORTD | ||||||||||||||||
| dsPIC33CKXXXMC502/102 | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| dsPIC33CKXXXMC503/103 | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| dsPIC33CKXXXMC505/105 | — | — | X | — | — | X | — | X | — | — | — | — | — | — | X | — |
| dsPIC33CKXXXMC506/106 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| ANSELD | — | — | X | — | — | X | — | — | — | — | — | — | — | — | — | — |