13.4.11.2 Ping-Pong Transmit Steady State

Figure 13-8 illustrates a ping-pong operation involving two connected DMA channels, as shown in Figure 13-7, alternately reading the CPU prepared data from the ping-pong buffers to a common peripheral responsible for transmitting the data. The CPU remains in full control of the operation without having to manually keep track of the DMA channel’s transactions. The CPU is free to perform other tasks until completion while the DMA is operating independently. When the CPU has completed its tasks, it simply enables the appropriate DMA channel via the CHEN bit. Given that the corresponding DMA channel has also completed its transfer and subsequently triggers the other DMA channel, the data flow exchange happens autonomously. When the DMA channel has completed its transfer, it asserts its trigger output signal, which enables the other DMA channel via PCHAEN (with PPEN set high). Note that when operating in Ping-Pong mode (PPEN = 1), both the CHEN and PCHAEN bits must be set high to enable the DMA channel.

In Figure 13-8, it is initially Channel 0 that completes its transaction while the CPU is still working on the buffer for Channel 1. Therefore, the data flow exchange happens after the CPU finishes and subsequently sets Channel 1's PCHAEN bit. Later on in the diagram, one can confirm that the data flow exchange does happen correctly if the CPU finishes while Channel 1 is still performing its transaction (reverse order).