13.4.11.5 Ping-Pong Receive Steady State

Figure 13-10 illustrates a ping-pong operation involving two DMA channels, connected as shown in Figure 13-9, alternately writing the data to the ping-pong buffers (FIFO) from a common peripheral responsible for receiving the data. The CPU remains in full control of the operation without having to manually keep track of the DMA channel’s transactions. The CPU is free to perform other tasks until completion while the DMA is operating independently. When the CPU has completed its tasks, it simply enables the appropriate DMA channel via the PCHAEN bit. When the DMA channel has completed its transfer, it asserts its trigger output signal, which enables the other DMA channel via PCHAEN (with PPEN set high). Note that when operating in Ping-Pong mode (PPEN = 1), both the CHEN and PCHAEN bits must be set high to enable the DMA channel. This allows the data flow exchange, which happens upon the next trigger by the receiving peripheral to be independent of the completion order.

Figure 13-10. Ping-Pong Receive Operation in Steady State
Note:
  1. DMA Channel 0 finishes before the CPU’s completion of its task, whereas DMA Channel 1 finishes after.
  2. Both the CHEN (Non-Repeated modes) and PCHAEN bits are hardware cleared once the transaction is completed.