27.3.1 Configurable Logic Cell x Control Register

Name: CLCxCON
Offset: 0x3A60, 0x3A70, 0x3A80, 0x3A90, 0x3AA0, 0x3AB0, 0x3AC0, 0x3AD0, 0x3AE0, 0x3AF0

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     G4POLG3POLG2POLG1POL 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
 ON   INTPINTN   
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
 LCOELCOUTLCPOL  MODE[2:0] 
Access R/WRRR/WR/WR/W 
Reset 000000 

Bit 19 – G4POL Gate 4 Polarity Control bit

ValueDescription
1 The output of Gate 4 logic is inverted when applied to the logic cell.
0 The output of Gate 4 logic is not inverted.

Bit 18 – G3POL Gate 3 Polarity Control bit

ValueDescription
1 The output of Gate 3 logic is inverted when applied to the logic cell.
0 The output of Gate 3 logic is not inverted.

Bit 17 – G2POL Gate 2 Polarity Control bit

ValueDescription
1 The output of Gate 2 logic is inverted when applied to the logic cell.
0 The output of Gate 2 logic is not inverted.

Bit 16 – G1POL Gate 1 Polarity Control bit

ValueDescription
1 The output of Gate 1 logic is inverted when applied to the logic cell.
0 The output of Gate 1 logic is not inverted.

Bit 15 – ON Configurable Logic Cell Enable bit

ValueDescription
1 Configurable Logic Cell is enabled and mixes input signals.
0 Configurable Logic Cell is disabled and has logic zero outputs.

Bit 11 – INTP Configurable Logic Cell Positive Edge Interrupt Enable bit

ValueDescription
1 Interrupt will be generated when a rising edge occurs on LCOUT.
0 Interrupt will not be generated.

Bit 10 – INTN Configurable Logic Cell Negative Edge Interrupt Enable bit

ValueDescription
1 Interrupt will be generated when a falling edge occurs on LCOUT.
0 Interrupt will not be generated.

Bit 7 – LCOE Configurable Logic Cell Port Enable bit

ValueDescription
1 Configurable Logic Cell port pin output is enabled.
0 Configurable Logic Cell port pin output is disabled.

Bit 6 – LCOUT Configurable Logic Cell Data Output Status bit

ValueDescription
1 Configurable Logic Cell output high
0 Configurable Logic Cell output low

Bit 5 – LCPOL Configurable Logic Cell Output Polarity Control bit

ValueDescription
1 The output of the module is inverted.
0 The output of the module is not inverted.

Bits 2:0 – MODE[2:0] Configurable Logic Cell Mode bits

ValueDescription
111 Cell is one-input transparent latch with S and R.
110 Cell is J-K flip-flop with Reset.
101 Cell is two-input D flip-flop with R.
100 Cell is one-input D flip-flop with S and R.
011 Cell is SR latch.
010 Cell is four-input AND.
001 Cell is OR-XOR.
000 Cell is AND-OR.