27.3.2 Configurable Logic Cell x Input MUX Select Register

Name:	CLCxSEL
Offset:	0x3A64, 0x3A74, 0x3A84, 0x3A94, 0x3AA4, 0x3AB4, 0x3AC4, 0x3AD4, 0x3AE4, 0x3AF4


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
		DS4[2:0]				DS3[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
		DS2[2:0]				DS1[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0

Bits 14:12 – DS4[2:0] Data Selection MUX 4 Signal Selection bits

See Table 27-5.

Bits 10:8 – DS3[2:0] Data Selection MUX 3 Signal Selection bits

See Table 27-4.

Bits 6:4 – DS2[2:0] Data Selection MUX 2 Signal Selection bits

See Table 27-3.

Bits 2:0 – DS1[2:0] Data Selection MUX 1 Signal Selection bits

See Table 27-2.

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