4.4.5.4 BMXxERR Registers

To properly deal with speculative data fetches, the BMXxERR registers have somewhat different behavior compared to standard error registers in other modules. When a bus error occurs, the BMX will always set the corresponding bit in the initiator’s BMXxERR register and set the bus error signal going to that initiator. However, the initiator may choose to do nothing about the bus error. This is most common in the case of the CPU when it is performing speculative fetches for data that never ends up getting used. If the erroneous data fetch is unused, there will be no trap or interrupt error event.

As a result, the BMX does not have clear information on when the BMXxERR error flags can safely be cleared, nor can it ensure a software routine will run that will be able to read and clear set flags. Therefore, to prevent past unused BMX error flags from staying set, the BMXxERR register will clear any previous flags whenever a new error event happens.

This effectively turns the BMXxERR register into a ‘one-hot’ register, where there will generally only be a single bit set at a time, reflecting the most recent error event. It is only possible for two bits to be set in the event that read and write errors occur simultaneously.