18.1 Device-Specific Information

Table 18-1. DAC Summary
DAC Module InstancesInputs per InstanceDAC OutputsClock SourcePeripheral Bus Speed
85 External, 1 Internal2CLKGEN7Standard
Table 18-2. High-Speed Analog Comparator Module Availability
Comparator Input48-Pin64-Pin80-Pin100-Pin128-Pin129-PinPPS
ALLCMPNCxxxxxxNo
ALLCMPNDxxxxxxNo
ALLCMPNExxxxxNo
ALLCMPNFxxxxxNo
ALLCMPPxxxxxxNo
CMPP1AxxxxxxNo
CMPP1BxxxxxxNo
CMPP1CxxxxxxNo
CMPP1DxxxxNo
CMPP2AxxxxxxNo
CMPP2BxxxxxxNo
CMPP2CxxxxxxNo
CMPP2D-xxxxxNo
CMPP3AxxxxxxNo
CMPP3BxxxxxxNo
CMPP3CxxxxxxNo
CMPP3DxxxxNo
CMPP4AxxxxxxNo
CMPP4BxxxxxxNo
CMPP4CxxxxxxNo
CMPP4DxxxxxxNo
CMPP5AxxxxxxNo
CMPP5BxxxxxxNo
CMPP5CxxxxxNo
CMPP5DxxxxNo
CMPP6AxxxxxxNo
CMPP6BxxxxxxNo
CMPP6C-xxxxxNo
CMPP7AxxxxxxNo
CMPP7BxxxxxNo
CMPP7CxxxNo
CMPP7DxxxxxxNo
CMPP8AxxxxxNo
CMPP8BxxxxNo
CMPP8CxxxNo
CMPP8DxxxxxNo
Table 18-3. Slope Start Signal Selection (SLPSTRT)
Slope Start Signal SelectionSource
15N/A
14RPV 15
13RPV 14
12APWM4
11APWM3
10APWM2
9APWM1
8PWM8
7PWM7
6PWM6
5PWM5
4PWM4
3PWM3
2PWM2
1PWM1
0N/A
Table 18-4. Slope Stop A Signal Select bits (SLPSTOPA)
Slope Stop A Signal SelectionSource
15N/A
14RPV 15
13RPV 14
12APWM4
11APWM3
10APWM2
9APWM1
8PWM8
7PWM7
6PWM6
5PWM5
4PWM4
3PWM3
2PWM2
1PWM1
0N/A
Table 18-5. Slope Stop B Signal Select bits (SLPSTOPB)
Slope Stop B Signal SelectionSource
15N/A
14RPV 15
13RPV 14
12APWM4
11APWM3
10APWM2
9APWM1
8PWM8
7PWM7
6PWM6
5PWM5
4PWM4
3PWM3
2PWM2
1PWM1
0N/A
Table 18-6. Hysteretic Comparator Function Input Select Bits (HCFSEL)
Hysterectic Comparator

Function Input Selection

Description
15N/A
14RPV 15
13RPV 14
12APWM4H
11APWM3H
10APWM2H
9APWM1H
8PWM8H
7PWM7H
6PWM6H
5PWM5H
4PWM4H
3PWM3H
2PWM2H
1PWM1H
0N/A

The calibration register FPDMDAC is located in Flash at 0x7F20E0 with the POSINLADJ, NEGINLADJ and DNLADJ bit fields. The location should be copied and written to the corresponding bit fields in the DACCTRL1 SFR at start up.

Table 18-7. FPDMDAC Calibration Register
NameAddress Offset

Bit Field

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

FPDMDAC0x00031:24cfg_dac_filter[3:0]
23:16POSINLADJ[5:0]
15:8NEGINLADJ[6:0]
7:0DNLADJ[4:0]