35.3.1.3 Idle Mode

Idle mode has the following characteristics:
  • The CPU stops executing instructions.
  • The system clock source remains active. The clock generators, controlled by the CLKGENx register, can be put into Idle mode by setting the corresponding SIDL bit. Note that the SIDL bit is unimplemented in the CLKGEN1 register. For more details, refer Oscillator Module.
  • The WDT is automatically cleared.
  • If the WDT or FSCM is enabled, the LPRC remains active.
  • The peripheral modules, by default, continue to operate normally from the system clock source.
  • Peripherals can optionally be shut down using their Stop-in-Idle (SIDL) control bit, which is located in bit position 13 of the control register for most peripheral modules. The generic bit field name format is “xxxSIDL” (where “xxx” is the mnemonic name of the peripheral device). For more details, refer to the respective peripheral sections in the data sheet.
  • The FRC Oscillator can be operated in Low-Power mode. This is controlled by the FRCLPWR[1:0] bits in the Oscillator Configuration register (OSCCFG[17:16]). For details, refer to Oscillator Module.
  • Flash can be put into Idle mode to reduce the power consumption. This is controlled by the NVMSIDL bit in the NVM Control register (NVMCON[12]). For details, refer to Flash Program Memory.

When the device exits Idle mode, the CPU starts executing instructions within eight system clock cycles.