9.3.9.1 Device Reset to Code Execution Start Time

The delay between the end of a Reset event and when the device actually begins to execute code is determined by two main factors: the type of Reset and the system clock source coming out of the Reset. The code execution start time for various types of device Resets are summarized in Table 9-2. Individual delays are characterized in Electrical Characteristics.

Table 9-2. Code Execution Start Time for Various Device Resets
Reset Type	Clock Source	Power-Up Delay^(1,2,3)	System Clock Delay^(4,5)	FSCM Delay⁽⁶⁾
POR	EC, FRC, FRCDIV, LPRC	(T_{pu or Tpwrt) + Tsysdly}	—	—
	ECPLL, FRCPLL	(T_{pu or Tpwrt) + Tsysdly}	T_lock	T_fscm
	XT, HS, SOSC	(T_{pu or Tpwrt) + Tsysdly}	T_ost	T_fscm
	XTPLL, HSPLL	(T_{pu or Tpwrt) + Tsysdly}	T_ost + T_lock	T_fscm
BOR	EC, FRC, FRCDIV, LPRC	_Tsysdly	—	—
	ECPLL, FRCPLL	_Tsysdly	T_lock	T_fscm
	XT, HS, SOSC	_Tsysdly	T_ost	T_fscm
	XTPLL	_Tsysdly	T_ost + T_lock	T_fscm
MCLR, CMR, SWR, WDTO, DMTO	Any Clock	Tsysdly	—	—
For parameter specifications, see Electrical Characteristics. Tpu = Power-up Period with on-chip regulator enabled Tpwrt = Power-up Period (Power-up Timer) with on-chip regulator disabled Tsysdly = Time required to reload Device Configuration Fuses plus eight SYSCLK cycles T_ost = Oscillator Start-up Timer T_lock= PLL lock time T_fscm = Fail-Safe Clock Monitor delay