Error Detection

The transmitter is responsible for calculating the parity bit value. Parity is always even, defined as the number of logic ones and the parity bit always being an even count. The receiver also calculates the parity value and compares it to the received parity bit. If a discrepancy is found, the error is flagged by the receiver, pulling the line low for a duration defined by the T0PD bit (UxSCCON[2]).

The transmitter tests the I/O line at time 11 ± 0.2 ETUs after the leading edge of the Start bit of a character was sent. If the transmitter detects an error by detecting a low state on the I/O line, it will repeat the disputed character after a delay of at least two ETUs following the detection of the error. The number of repeats is configured with the TXRPT[1:0] bits (UxSCCON[5:4]). See Figure 20-18 for timing details in T = 0 mode.

Figure 20-18. T = 0 Character Repetition Timing
Note:
  1. 8-bit character
  2. At 10.0 ± 0.2 ETUs, the transmitter disables the driver.
  3. At 10.5 ± 0.2 ETUs, the receiver sets the I/O line low if a parity error is detected.
  4. At 11.0 ± 0.2 ETUs, the transmitter tests the I/O line.
  5. See the T0PD bit (UxSCCON[2]) in UxSCCON.