21.4.1.8.4 SPI Host Mode and Frame Client Mode

This Framed SPI mode is enabled by setting the MSTEN bit (SPIxCON1[5]), the FRMEN bit (SPIxCON1[23]) and the FRMSYNC bit (SPIxCON1[22]) to ‘1’. The SSx pin is an input and it is sampled on the sample edge of the SPI clock. When it is sampled active-high or active-low, depending on the FRMPOL bit (SPIxCON1[21]), data will be transmitted on the subsequent transmit edge of the SPI clock, as shown in Figure 21-14. The SPIx Interrupt Flag, SPIxIF, is set when the transmission is complete. The user must make sure that the correct data are loaded into SPIxBUF for transmission before the signal is received at the SSx pin. A connection diagram indicating signal directions for this operating mode is shown in Figure 21-15.