9.2.1 Reset Control Register
Legend: R = Readable bit, C = Clearable bit, HS = Hardware Settable bit
| Name: | RCON |
| Offset: | 0x31A0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VREG4R | VREG3R | VREG2R | BUCKR | ||||||
| Access | R/C/HS | R/C/HS | R/C/HS | R/C/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CM | |||||||||
| Access | R/C/HS | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTR | SWR | WDTO | SLEEP | IDLE | BOR | POR | |||
| Access | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R/C/HS | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
Bit 22 – VREG4R VREG Voltage Regulator 4 Flag bit
| Value | Description |
|---|---|
1 |
Voltage Domain 4 lost voltage and a Reset has occurred. |
0 |
Voltage Regulation in Domain 4 remains intact. |
Bit 21 – VREG3R VREG Voltage Regulator 3 Flag bit
| Value | Description |
|---|---|
1 |
Voltage Domain 3 lost voltage and a Reset has occurred. |
0 |
Voltage Regulation in Domain 3 remains intact. |
Bit 20 – VREG2R VREG Voltage Regulator 2 Flag bit
| Value | Description |
|---|---|
1 |
Voltage Domain 2 lost voltage and a Reset has occurred. |
0 |
Voltage Regulation in Domain 2 remains intact. |
Bit 18 – BUCKR Buck Converter Flag bit
| Value | Description |
|---|---|
1 |
Buck regulation lost voltage regulation. |
0 |
Buck regulation remains intact. |
Bit 9 – CM Configuration Mismatch Flag bit
| Value | Description |
|---|---|
1 |
A Configuration Mismatch Reset has occurred. |
0 |
A Configuration Mismatch Reset has not occurred. |
Bit 7 – EXTR External Reset (MCLR) Pin bit
| Value | Description |
|---|---|
1 |
A Master Clear (pin) Reset has occurred. |
0 |
A Master Clear (pin) Reset has not occurred. |
Bit 6 – SWR Software Reset (Instruction) Flag bit
| Value | Description |
|---|---|
1 |
A |
0 |
A |
Bit 4 – WDTO Watchdog Timer Time-out Flag bit
| Value | Description |
|---|---|
1 |
Device Reset has occurred due to WDT time-out. |
0 |
WDT time-out has not occurred. |
Bit 3 – SLEEP Wake-up from Sleep Flag bit
| Value | Description |
|---|---|
1 |
Device has been in Sleep mode. |
0 |
Device has not been in Sleep mode. |
Bit 2 – IDLE Wake-up from Idle Flag bit
| Value | Description |
|---|---|
1 |
Device has been in Idle mode. |
0 |
Device has not been in Idle mode. |
Bit 1 – BOR Brown-out Reset Flag bit
| Value | Description |
|---|---|
1 |
A Brown-out Reset has occurred. Set by hardware at detection of a BOR event. |
0 |
A Brown-out Reset has not occurred. |
Bit 0 – POR Power-on Reset Flag bit
| Value | Description |
|---|---|
1 |
A Power-on Reset has occurred. Set by hardware at detection of a POR event. |
0 |
A Power-on Reset has not occurred. |