25.3.1 Timer x Control Register
Note:
- When Timer x is enabled in
External Synchronous Counter mode (TCS =
1, TSYNC =1, TON =1), any attempts by user software to write to the TMR1 register are ignored.
| Name: | TxCON |
| Offset: | 0x1CE0, 0x1CF0, 0x1D00 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | TMWDIS | TMWIP | PRWIP | |||||
| Access | R/W | R/W | R/W | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TGATE | TCKPS[1:0] | TSYNC | TCS | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 15 – ON Timer On bit(1)
| Value | Description |
|---|---|
1 |
Starts 32-bit Timer |
0 |
Stops 32-bit Timer |
Bit 13 – SIDL Timer Stop in Idle Mode bit
| Value | Description |
|---|---|
1 |
Discontinues the module operation when the device enters Idle mode. |
0 |
Continues the module operation in Idle mode. |
Bit 12 – TMWDIS Asynchronous Timer Write Disable bit
| Value | Description |
|---|---|
1 |
Timer writes are ignored while a posted write to TMRx or PRx is synchronized to the asynchronous clock domain |
0 |
Back-to-back writes are enabled in Asynchronous mode |
Bit 11 – TMWIP Asynchronous Timer Write in Progress bit
| Value | Description |
|---|---|
1 |
Write to the timer in Asynchronous mode is pending. |
0 |
Write to the timer in Asynchronous mode is complete. |
Bit 10 – PRWIP Asynchronous Period Write in Progress bit
| Value | Description |
|---|---|
1 |
Write to the Period register in Asynchronous mode is pending. |
0 |
Write to the Period register in Asynchronous mode is complete. |
Bit 7 – TGATE Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
| Value | Description |
|---|---|
1 |
Gated time accumulation is enabled. |
0 |
Gated time accumulation is disabled. |
Bits 5:4 – TCKPS[1:0] Timer Input Clock Prescale Select bits
| Value | Description |
|---|---|
11 |
1:256 |
10 |
1:64 |
01 |
1:8 |
00 |
1:1 |
Bit 2 – TSYNC Timer External Clock Input Synchronization Select bit(1)
When TCS = 0:
This bit is ignored.
When TCS =1:| Value | Description |
|---|---|
1 |
Synchronizes the external clock input. |
0 |
Does not synchronize the external clock input. |
