25.3 Register Summary


Offset	Name	Bit Pos.	7	5	4	3	2	1
0x1CE0	T1CON	31:24
		23:16
		15:8	ON	SIDL	TMWDIS	TMWIP	PRWIP
		7:0	TGATE	TCKPS[1:0]			TSYNC	TCS
0x1CE4	TMR1	31:24	TMR[31:24]
		23:16	TMR[23:16]
		15:8	TMR[15:8]
		7:0	TMR[7:0]
0x1CE8	PR1	31:24	PR[31:24]
		23:16	PR[23:16]
		15:8	PR[15:8]
		7:0	PR[7:0]
0x1CEC ... 0x1CEF	Reserved
0x1CF0	T2CON	31:24
		23:16
		15:8	ON	SIDL	TMWDIS	TMWIP	PRWIP
		7:0	TGATE	TCKPS[1:0]			TSYNC	TCS
0x1CF4	TMR2	31:24	TMR[31:24]
		23:16	TMR[23:16]
		15:8	TMR[15:8]
		7:0	TMR[7:0]
0x1CF8	PR2	31:24	PR[31:24]
		23:16	PR[23:16]
		15:8	PR[15:8]
		7:0	PR[7:0]
0x1CFC ... 0x1CFF	Reserved
0x1D00	T3CON	31:24
		23:16
		15:8	ON	SIDL	TMWDIS	TMWIP	PRWIP
		7:0	TGATE	TCKPS[1:0]			TSYNC	TCS
0x1D04	TMR3	31:24	TMR[31:24]
		23:16	TMR[23:16]
		15:8	TMR[15:8]
		7:0	TMR[7:0]
0x1D08	PR3	31:24	PR[31:24]
		23:16	PR[23:16]
		15:8	PR[15:8]
		7:0	PR[7:0]