13.4.13.1 Real-Time Matching
The MATEN bit (DMAxCH[2]) is used to enable the feature per selected channel; see DMAxCH. Once enabled, the contents of DMABUF[31:0] and DMAxPAT[31:0] are subjected to the corresponding DMAxMSK[31:0] bits value and compared against each other in an array of two input digital comparators, as shown below. When a match is detected, the DMA Controller proceeds to invoke its channel interrupt output while setting the MATCH bit (DMAxSTAT[1]), accordingly. Note that the DMA operation continues until completion, unaffected by the real-time matching. Upon interrupt detection by the CPU, the user’s software is expected to start processing the incoming data until it comes across the pattern. It may also be necessary to update the DMAxPAT[31:0]/DMAxMSK[31:0] bits for proper pattern matching associated with the current incoming data stream.
- When a match is first detected, the data still reside in the Data Buffer register. Depending on the bus infrastructure, it takes a varying number of clock cycles for it to reach the destination. It is up to the user’s software to manage this latency period to properly recover the correct data.
- It is up to the user’s software to timely clear the MATCH bit (DMAxSTAT[1]) in order to prevent an overrun-like condition, where multiple matches occur with no CPU response. Currently, there is no capability to flag this condition.
- The pattern match feature does not take SIZE[1:0] into account, so it is left to the user’s software to set the mask accordingly.