13.3.5 DMA Channel x Control Register

Legend: HS = Hardware Settable bit, HC = Hardware Clearable bit

Note:

The number of transfers per CHREQ bit setting depends on TRMODE[1:0].
The channel enable also depends on PCHAEN if PPEN is set high for ping-pong operation support.
CNT[31:0] are reloaded in every repeated operation regardless of RELOADC.

Name:	DMAxCH
Offset:	0x2310, 0x233C, 0x2368, 0x2394, 0x23C0, 0x23EC, 0x2418, 0x2444


Bit	31	30	29	28	27	26	25	24
			PPEN	PCHAEN		RELOADC	RELOADD	RELOADS
Access			R/W	R/W/HS/HC		R/W	R/W	R/W
Reset			0	0		0	0	0


Bit	23	22	21	20	19	18	17	16
								RETEN
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
	SAMODE[1:0]		DAMODE[1:0]		TRMODE[1:0]		FLWCON[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SIZE[1:0]			CHREQ	DONEEN	MATEN	HALFEN	CHEN
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W/HC
Reset	0	0		0	0	0	0	0

Bit 29 – PPEN Ping-Pong Operation Support Enable bit (refer to Ping-Pong)

Value	Description
1	Ping-pong operation support is enabled.
0	Ping-pong operation support is disabled.

Bit 28 – PCHAEN Ping-Pong Channel Enable bit (refer to Ping-Pong)

Intended to support the ping-pong operation; the bit takes effect only when PPEN is set high as follows.

Value	Description
1	The DMA channel is enabled if CHEN is set high; this bit is hardware settable via PCHAEN of the other DMA channel pair used in the Ping-Pong mode.
0	The DMA channel is disabled.

Bit 26 – RELOADC CNT[31:0] Reload bit⁽³⁾

Value	Description
1	CNT[31:0] are reloaded to their previously written value (buffered original content) upon the start of the next operation.
0	CNT[31:0] are not reloaded.

Bit 25 – RELOADD DADDR[23:0] Reload bit

Value	Description
1	DADDR[23:0] are reloaded to their previously written value upon the start of the next operation.
0	DADDR[23:0] are not reloaded.

Bit 24 – RELOADS SADDR[23:0] Reload bit

Value	Description
1	SADDR[23:0] are reloaded to their previously written value upon the start of the next operation.
0	SADDR[23:0] are not reloaded.

Bit 16 – RETEN Read Error Trap Enable bit

Value	Description
1	DMA channel suspends transfer operation on bus read error and asserts dma_trap signal.
0	DMA channel continues transfer operation when bus read error is encountered.

Bits 15:14 – SAMODE[1:0] Source Address Mode Selection bits

Value	Description
11	Reserved
10	SADDR[23:0] are decremented based on SIZE[1:0] after a transfer completion.
01	SADDR[23:0] are incremented based on SIZE[1:0] after a transfer completion.
00	SADDR[23:0] remain unchanged after a transfer completion.

Bits 13:12 – DAMODE[1:0] Destination Address Mode Selection bits

Value	Description
11	Reserved
10	DADDR[23:0] are decremented based on SIZE[1:0] after a transfer completion.
01	DADDR[23:0] are incremented based on SIZE[1:0] after a transfer completion.
00	DADDR[23:0] remain unchanged after a transfer completion.

Bits 11:10 – TRMODE[1:0] Transfer Mode Selection bits

Value	Description
11	Repeated Continuous
10	Continuous
01	Repeated One-Shot
00	One-Shot

Bits 9:8 – FLWCON[1:0] Data Flow Control bits

Value	Description
11	Reserved
10	Read from SADDR[23:0] only
01	Read from SADDR[23:0] followed by write to DADDR[23:0] and SADDR[23:0] (`NULLW`)
00	Read from SADDR[23:0] followed by write to DADDR[23:0]

Bits 7:6 – SIZE[1:0] Data Size Selection bits

Value	Description
11	Reserved
10	One 32-bit word is transferred at a time.
01	One 16-bit word is transferred at a time.
00	One byte word is transferred at a time.

Bit 4 – CHREQ DMA Channel Software Request bit⁽¹⁾

This bit is automatically reset to ‘0’ upon completion of a DMA transfer.

Value	Description
1	One DMA request is initiated by software.
0	No DMA request is initiated by software.

Bit 3 – DONEEN Done Interrupt Enable bit

Value	Description
1	An interrupt is invoked upon DONE flag being set.
0	An interrupt is not invoked by DONE condition.

Bit 2 – MATEN Pattern Match Enable bit

Value	Description
1	Pattern match is enabled.
0	Pattern match is disabled.

Bit 1 – HALFEN 50% Completion Watermark bit

Value	Description
1	An interrupt is invoked when the CNT[31:0] counter has reached its halfway point.
0	An interrupt is not invoked by a Half condition.

Bit 0 – CHEN DMA Channel Enable bit ⁽²⁾

Value	Description
1	The corresponding DMA channel is enabled.
0	The corresponding DMA channel is disabled.