22.5.2.5 Generating a Stop Bus Event

Setting the PEN bit (I2CxCON1[2]) enables the generation of a host Stop sequence.

Note: The lower five bits of the I2CxCON1 register must be ‘0’ (host logic inactive) before attempting to set the PEN bit.

When the PEN bit is set, the host generates the Stop sequence, as illustrated in Figure 22-12.

The client detects the Stop condition, sets the P status bit (I2CxSTAT1[4]) and clears the S status bit (I2CxSTAT1[3]).
STOPE(I2CxSTAT2[15]) bit is set.
The PEN bit is automatically cleared.
The HSTACT( I2CxSTAT2[29]) bit is cleared when the STOP is sent.
The module generates the I2CxIF interrupt if the HPCIE(I2CxINTC[28]) bit and HSTIE(I2CxINTC[13]) are enabled.

Note: Because queuing of events is not allowed, writing to the lower five bits of the I2CxCON1 register is disabled until the Stop condition is complete.

Figure 22-12. Host Stop Timing Diagram