20.4.2.1.1 Asynchronous Transmit

The transmitter block diagram of the UART module is illustrated in Figure 20-8. The important part of the transmitter is the UARTx Transmit Shift Register (UxTSR). The Shift register obtains its data from the transmit FIFO buffer, UxTXB. The UxTXB register is loaded with data in software.

The UxTSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the UxTSR is loaded with new data from the UxTXB register, if available.

Note: The UxTSR register is not mapped in data memory, so it is not available to the user application.

The transmission is enabled by setting the TXEN enable bit (UxCON[5]). The actual transmission will not occur until the UxTXB register has been loaded with data and the Baud Rate Generator (UxBRG) has produced a shift clock (Figure 20-8). Normally, when the first transmission is started, the UxTSR register is empty, so a transfer to the UxTXB register will result in an immediate transfer to UxTSR when the TXEN bit is set. When the TXEN bit is written to ‘0’, the transmit process ends at the end of the current byte. As a result, the UxTX pin will revert to a High-Impedance state.

Figure 20-8. Asynchronous Transmitter Block Diagram

Note: ‘x’ denotes the UART number.