3.5.1 Device-Specific Information

Table 3-10. Performance Monitor Summary
Number of counters	Peripheral Bus Speed	Clock Source
8	Standard	Standard Speed Peripheral Clock

Table 3-11. Counter Event Source Selection
SELECT n [4:0]	Event source	Note
18	Fetch stage PBU miss	This event indicates that the requested program data could not be sourced from either the cache memory or the ISB. Therefore, a new fetch from program memory with additional execution cycles was required to obtain the data.
17	Fetch stage PBU hit	This event indicates that the requested program data was sourced from either the cache memory or the ISB. Therefore, no additional execution cycles were required to fetch the instruction.
16	Fetch stage cache busy	Indicates a cycle when the cache was busy transferring data from the instruction stream buffer (ISB) to the cache memory.
15	Fetch stage program memory vector fetch	Indicates that the CPU fetches an interrupt vector and is aligned with a Program Flow Change event. This event can be used to count interrupt events.
14	Fetch stage program memory program flow change	Indicates that a change in program flow has occurred. This could be due to a CALL, RETURN, RETFIE, conditional or unconditional branch, or interrupt event.
13	Fetch stage read stall	Indicates an extra cycle is needed to fetch a program word from memory. This could be caused by a cache miss or an arbitration conflict when fetching program words and data from the same memory.
12	Fetch stage interrupt latency count enable	Indicates the number of cycles due to interrupt latency.
11	Address stage stall	Indicates that CPU pipeline was stalled in the Address stage for any reason, possibly because the instruction is being discarded.
10	Address stage read stall	Indicates that an instruction could not continue because of an extra latency reading a RAM or SFR location.
9	Address stage FPU read stall	Indicates that CPU execution is presently stalled because the CPU cannot read from a FPU register. This occurs because the FPU is currently busy updating the register data.
8	Address stage FPU instruction stall	Indicates that execution in the FPU coprocessor is currently stalled due to a register data dependency.
7	Address stage hazard	Indicates an extra execution cycle caused by a data dependency upon an earlier instruction in the CPU pipeline, which could not be forwarded.
6	Read stage branch mispredict	Indicates an extra execution cycle caused by mispredicted program flow changes.
5	Read stage conditional branch	Indicates the occurrence of a conditional branch instruction. The count of conditional branch instructions can be compared to the number of branch mispredictions in order to determine the effectiveness of the CPU branch prediction logic.
4	Write stage stall	Indicates that an instruction could not continue because of an extra latency writing to RAM or SFRs.
3	Write stage FPU stall	Indicates that CPU execution is presently stalled because the CPU cannot write to the FPU registers. This occurs because the FPU is currently busy working on the existing register data.
2	CPU instruction completed	Indicates that an instruction in the CPU pipeline has completed.
1	CPU cycle elapsed (reference)	This event count provides the total number of CPU clock cycles elapsed.
0	None

18

Fetch stage PBU miss

This event indicates that the requested program data could not be sourced from either the cache memory or the ISB. Therefore, a new fetch from program memory with additional execution cycles was required to obtain the data.

17

Fetch stage PBU hit

This event indicates that the requested program data was sourced from either the cache memory or the ISB. Therefore, no additional execution cycles were required to fetch the instruction.

16

Fetch stage cache busy

Indicates a cycle when the cache was busy transferring data from the instruction stream buffer (ISB) to the cache memory.

15

Fetch stage program memory vector fetch

Indicates that the CPU fetches an interrupt vector and is aligned with a Program Flow Change event. This event can be used to count interrupt events.

14

Fetch stage program memory program flow change

Indicates that a change in program flow has occurred. This could be due to a CALL, RETURN, RETFIE, conditional or unconditional branch, or interrupt event.

13

Fetch stage read stall

Indicates an extra cycle is needed to fetch a program word from memory. This could be caused by a cache miss or an arbitration conflict when fetching program words and data from the same memory.

12

Fetch stage interrupt latency count enable

Indicates the number of cycles due to interrupt latency.

11

Address stage stall

Indicates that CPU pipeline was stalled in the Address stage for any reason, possibly because the instruction is being discarded.

10

Address stage read stall

Indicates that an instruction could not continue because of an extra latency reading a RAM or SFR location.

9

Address stage FPU read stall

Indicates that CPU execution is presently stalled because the CPU cannot read from a FPU register. This occurs because the FPU is currently busy updating the register data.

8

Address stage FPU instruction stall

Indicates that execution in the FPU coprocessor is currently stalled due to a register data dependency.

7

Address stage hazard

Indicates an extra execution cycle caused by a data dependency upon an earlier instruction in the CPU pipeline, which could not be forwarded.

6

Read stage branch mispredict

Indicates an extra execution cycle caused by mispredicted program flow changes.

5

Read stage conditional branch

Indicates the occurrence of a conditional branch instruction. The count of conditional branch instructions can be compared to the number of branch mispredictions in order to determine the effectiveness of the CPU branch prediction logic.

4

Write stage stall

Indicates that an instruction could not continue because of an extra latency writing to RAM or SFRs.

3

Write stage FPU stall

Indicates that CPU execution is presently stalled because the CPU cannot write to the FPU registers. This occurs because the FPU is currently busy working on the existing register data.

2

CPU instruction completed

Indicates that an instruction in the CPU pipeline has completed.

1

CPU cycle elapsed (reference)

This event count provides the total number of CPU clock cycles elapsed.

0

None