2.9.6.2.1 Using PDC

To select the DDR subsystem location, add the following PDC constraint to the floor planner constraints:

set_location -inst_name <memory component inst name> -location <edge>_<anchor>

For example, set_location –inst_name {PF_DDR3_C0_0} –location {NORTH_NE}.

The number of I/Os per bank varies from package to package; therefore, the maximum DDR memory width supported by each bank is not same for all packages in the PolarFire family. For more information, see the respective user guides as follows:

• UG0722: PolarFire FPGA Packaging and Pin Descriptions User Guide
• UG0902: PolarFire SoC FPGA Packaging and Pin Descriptions User Guide