Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk_T2) is therefore shown as a clock enable signal. In Asynchronous mode, clk_I/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 1. Timer/Counter Timing Diagram, no Prescaling

The next figure shows the same timing data, but with the prescaler enabled.

Figure 2. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

The next figure shows the setting of OCF2 in all modes except CTC mode.

Figure 3. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f_{clk_I/O}/8)

The figure below shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.

Figure 4. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f_{clk_I/O}/8)