38.6.11 ADC Interrupt Disable Register
This register can only be written if the WPITEN bit is cleared in the ADC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
| Name: | ADC_IDR |
| Offset: | 0x28 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | COMPE | GOVRE | DRDY | |
| Access | | | | | | W | W | W | |
| Reset | | | | | | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | TEMPCHG | EOS | | | |
| Access | | | | | W | W | | | |
| Reset | | | | | – | – | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | RXOVR | RXUDR | RXCHUNK | RXFULL | RXEMPTY | RXRDY | |
| Access | | | W | W | W | W | W | W | |
| Reset | | | – | – | – | – | – | – | |
Bit 26 – COMPE Comparison Event Interrupt Disable
Bit 25 – GOVRE General Overrun Error Interrupt Disable
Bit 24 – DRDY Data Ready Interrupt Disable
Bit 19 – TEMPCHG Temperature Change Interrupt Disable
Bit 18 – EOS End Of Sequence Interrupt Disable
Bit 5 – RXOVR Receive Over Flow Interrupt Disable
Bit 4 – RXUDR Receive Under Flow Interrupt Disable
Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt
Disable
Bit 2 – RXFULL Receive FIFO Full Interrupt Disable
Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Disable
Bit 0 – RXRDY Receive Ready Interrupt Disable
