38.6.10 ADC Interrupt Enable Register

This register can only be written if the WPITEN bit is cleared in the ADC Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name:	ADC_IER
Offset:	0x24
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24
						COMPE	GOVRE	DRDY
Access						W	W	W
Reset						–	–	–


Bit	23	22	21	20	19	18	17	16
					TEMPCHG	EOS
Access					W	W
Reset					–	–


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
Access			W	W	W	W	W	W
Reset			–	–	–	–	–	–

Bit 26 – COMPE Comparison Event Interrupt Enable

Bit 25 – GOVRE General Overrun Error Interrupt Enable

Bit 24 – DRDY Data Ready Interrupt Enable

Bit 19 – TEMPCHG Temperature Change Interrupt Enable

Bit 18 – EOS End Of Sequence Interrupt Enable

Bit 5 – RXOVR Receive Over Flow Interrupt Enable

Bit 4 – RXUDR Receive Under Flow Interrupt Enable

Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt Enable

Bit 2 – RXFULL Receive FIFO Full Interrupt Enable

Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Enable

Bit 0 – RXRDY Receive Ready Interrupt Enable

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