38.6.5 ADC Channel Enable Register
If ADC_MR.USEQ = 1, CHx corresponds to the enable of sequence number x+1 described in ADC_SEQR1 and ADC_SEQR2 (for example, CH0 enables sequence number USCH1). For example, if Differential mode is required on channel 0, input pins AD0 and AD1 are used. In this case, only channel 0 must be enabled by writing a 1 to ADC_CHER.CH0.
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_CHER |
| Offset: | 0x10 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CH31 | CH30 | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CH15 | CH14 | CH13 | CH12 | CH11 | CH10 | CH9 | CH8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CH7 | CH6 | CH5 | CH4 | CH3 | CH2 | CH1 | CH0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 30, 31 – CH30, CH31 Channel x Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the corresponding channel. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CHx Channel x Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the corresponding channel. |