38.6.23 ADC Channel Configuration Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_CCR |
| Offset: | 0x5C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIFF15 | DIFF14 | DIFF13 | DIFF12 | DIFF11 | DIFF10 | DIFF9 | DIFF8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIFF7 | DIFF6 | DIFF5 | DIFF4 | DIFF3 | DIFF2 | DIFF1 | DIFF0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – DIFFx Differential Inputs for Channel x
| Value | Description |
|---|---|
| 0 | Corresponding channel is set in Single-ended mode. |
| 1 | Corresponding channel is set in Differential mode. |