38.6.15 ADC End Of Conversion Interrupt Disable Register
This register can only be written if the WPITEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_EOC_IDR |
| Offset: | 0x38 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EOC31 | EOC30 | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EOC15 | EOC14 | EOC13 | EOC12 | EOC11 | EOC10 | EOC9 | EOC8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 30, 31 – EOC30, EOC31 End of Conversion Interrupt Disable x
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the corresponding interrupt. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EOCx End of Conversion Interrupt Disable x
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the corresponding interrupt. |