38.6.25 ADC Analog Control Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
By default, bits 12 and 13 are set to 1 and 0, respectively, and must not be modified.
| Name: | ADC_ACR |
| Offset: | 0xE0 |
| Reset: | 0x00000100 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SRCLCH | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IBCTL[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 1 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 16 – SRCLCH Source Last Channel
| Value | Name | Description |
|---|---|---|
| 0 | VTEMP |
The highest index channel is driven by the output of the temperature sensor. |
| 1 | VBG |
The highest index channel is driven by the reference voltage of the temperature sensor. |
Bits 9:8 – IBCTL[1:0] ADC Bias Current Control
Adapts performance versus power consumption. Refer to the section “Electrical Characteristics” for further details.