38.6.12 ADC Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
| Name: | ADC_IMR |
| Offset: | 0x2C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | COMPE | GOVRE | DRDY | |
| Access | | | | | | R | R | R | |
| Reset | | | | | | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | TEMPCHG | EOS | | | |
| Access | | | | | R | R | | | |
| Reset | | | | | 0 | 0 | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | RXOVR | RXUDR | RXCHUNK | RXFULL | RXEMPTY | RXRDY | |
| Access | | | R | R | R | R | R | R | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 26 – COMPE Comparison Event Interrupt
Mask
Bit 25 – GOVRE General Overrun Error Interrupt
Mask
Bit 24 – DRDY Data Ready Interrupt Mask
Bit 19 – TEMPCHG Temperature Change Interrupt
Disable
Bit 18 – EOS End Of Sequence Interrupt
Mask
Bit 5 – RXOVR Receive Over Flow Interrupt Mask
Bit 4 – RXUDR Receive Under Flow Interrupt Mask
Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt
Mask
Bit 2 – RXFULL Receive FIFO Full Interrupt Mask
Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Mask
Bit 0 – RXRDY Receive Ready Interrupt Mask
