38.6.13 ADC Interrupt Status Register
| Name: | ADC_ISR |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| COMPE | GOVRE | DRDY | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TEMPCHG | EOS | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXOVR | RXUDR | RXCHUNK | RXFULL | RXEMPTY | RXRDY | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 26 – COMPE Comparison Event (cleared on read)
| Value | Description |
|---|---|
| 0 | No comparison event occurred since the last read of ADC_ISR. |
| 1 | At least one comparison event (defined in ADC_EMR and ADC_CWR) has occurred since the last read of ADC_ISR. |
Bit 25 – GOVRE General Overrun Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No general overrun error occurred since the last read of ADC_ISR. |
| 1 | At least one general overrun error has occurred since the last read of ADC_ISR. |
Bit 24 – DRDY Data Ready (automatically set / cleared)
| Value | Description |
|---|---|
| 0 | No data has been converted since the last read of ADC_LCDR. |
| 1 | At least one data has been converted and is available in ADC_LCDR. |
Bit 19 – TEMPCHG Temperature Change (cleared on read)
| Value | Description |
|---|---|
| 0 | There is no comparison match (defined in the Temperature Compare Window register (ADC_TEMPCWR) since the last read of ADC_ISR. |
| 1 | The temperature value reported on ADC_CDRmax (max=highest index) has changed since the last read of ADC_ISR, according to what is defined in ADC_TEMPTMR and ADC_TEMPCWR. |
Bit 18 – EOS End Of Sequence (cleared on read)
| Value | Description |
|---|---|
| 0 | No sequence is in progress or the sequence is not finished. This flag is cleared when reading ADC_ISR. |
| 1 | The sequence is complete. |
Bit 5 – RXOVR Receive Over Flow (cleared on read)
| Value | Description |
|---|---|
| 0 | No general overrun error occurred since the last read of ADC_ISR. |
| 1 | At least one general overrun error has occurred since the last read of ADC_ISR. |
Bit 4 – RXUDR Receive Under Flow (cleared on read)
| Value | Description |
|---|---|
| 0 | No general underrun error occurred since the last read of ADC_ISR. |
| 1 | At least one general underrun error has occurred since the last read of ADC_ISR. |
Bit 3 – RXCHUNK Receive FIFO Chunk (cleared on read)
| Value | Description |
|---|---|
| 0 |
The number of written elements in the FIFO has been lower than or not equal to chunk_size since the last read of ADC_ISR. |
| 1 |
The number of written elements in the FIFO has been greater than or equal to chunk_size since the last read of ADC_ISR. |
Bit 2 – RXFULL Receive FIFO Full (cleared on read)
| Value | Description |
|---|---|
| 0 | FIFO has not been full since the last read of ADC_ISR. |
| 1 | FIFO has been full since the last read of ADC_ISR. |
Bit 1 – RXEMPTY Receive FIFO Empty (cleared on read)
| Value | Description |
|---|---|
| 0 | FIFO has not been empty since the last read of ADC_ISR. |
| 1 | FIFO has been empty since the last read of ADC_ISR. |
Bit 0 – RXRDY Receive Ready (cleared on read)
| Value | Description |
|---|---|
| 0 | FIFO has been empty since the last read of ADC_ISR. |
| 1 | One element has been written since the last read of ADC_ISR. |