38.6.21 ADC Extended Mode Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
Name: | ADC_EMR |
Offset: | 0x50 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
ALTCH | ADCMODE[1:0] | SIGNMODE[1:0] | TAG | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TRACKX[1:0] | ALWAYS0 | ASTE | OSR[2:0] | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CMPFILTER[1:0] | CMPALL | CMPSEL[4] | |||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CMPSEL[3:0] | CMPTYPE | CMPMODE[1:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 30 – ALTCH Alternate Channel Selection (Safety)
Value | Description |
---|---|
0 | The regular channels are selected. |
1 | The alternate channels are selected. |
Bits 29:28 – ADCMODE[1:0] ADC Running Mode
See Automatic Error Correction for details on ADC Running mode.
Value | Name | Description |
---|---|---|
0 | NORMAL | Normal mode of operation. |
1 | OFFSET_ERROR | Offset Error mode to measure the offset error. See the table ADC Running Modes. |
2 | GAIN_ERROR_HIGH | Gain Error mode to measure the gain error. See the table ADC Running Modes. |
3 | GAIN_ERROR_LOW | Gain Error mode to measure the gain error. See the table ADC Running Modes. |
Bits 26:25 – SIGNMODE[1:0] Sign Mode
If conversion results are signed and resolution is below 16 bits, the sign is extended up to bit 15 (for example, 0xF43 for 12-bit resolution is read as 0xFF43 and 0x467 is read as 0x0467). See Conversion Results Format.
Value | Name | Description |
---|---|---|
0 | SE_UNSG_DF_SIGN | Single-ended channels: unsigned conversions Differential channels: signed conversions |
1 | SE_SIGN_DF_UNSG | Single-ended channels: signed conversions Differential channels: unsigned conversions |
2 | ALL_UNSIGNED | All channels: unsigned conversions |
3 | ALL_SIGNED | All channels: signed conversions |
Bit 24 – TAG ADC_LCDR Tag
Value | Description |
---|---|
0 | Sets ADC_LCDR.NO_OSR_CHNB/CHNBOSR to zero. |
1 | Appends the channel number to the conversion result in ADC_LCDR. |
Bits 23:22 – TRACKX[1:0] Tracking Time x4, x8 or x16
Value | Name | Description |
---|---|---|
0 | TRACKTIMx1 | ADC_MR.TRACKTIM effect is multiplied by 1. |
1 | TRACKTIMx4 | ADC_MR.TRACKTIM effect is multiplied by 4. |
2 | TRACKTIMx8 | ADC_MR.TRACKTIM effect is multiplied by 8. |
3 | TRACKTIMx16 | ADC_MR.TRACKTIM effect is multiplied by 16. |
Bit 21 – ALWAYS0 Must always be written to 0
Bit 20 – ASTE Averaging on Single Trigger Event
Value | Name | Description |
---|---|---|
0 | MULTI_TRIG_AVERAGE | The average requests several trigger events. |
1 | SINGLE_TRIG_AVERAGE | The average requests only one trigger event. |
Bits 18:16 – OSR[2:0] Over Sampling Rate
Value | Name | Description |
---|---|---|
0 | NO_AVERAGE | No averaging. ADC sample rate is maximum. |
1 | OSR4 | 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. |
2 | OSR16 | 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. |
3 | OSR64 | 3-bit enhanced resolution by averaging. ADC sample rate divided by 64. |
4 | OSR256 | 4-bit enhanced resolution by averaging. ADC sample rate divided by 256. |
Bits 13:12 – CMPFILTER[1:0] Compare Event Filtering
Number of consecutive compare events necessary to raise the flag = CMPFILTER+1
When programmed to 0, the flag rises as soon as an event occurs.
See Comparison Window when using the filtering option (CMPFILTER > 0).
Bit 9 – CMPALL Compare All Channels
Value | Description |
---|---|
0 | Only the channel indicated in CMPSEL is compared. |
1 | All channels are compared. |
Bits 8:4 – CMPSEL[4:0] Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
Bit 2 – CMPTYPE Comparison Type
Value | Name | Description |
---|---|---|
0 | FLAG_ONLY | Any conversion is performed and comparison function drives the COMPE flag. |
1 | START_CONDITION | Comparison conditions must be met to start the storage of all conversions until ADC_CR.CMPRST is set. |
Bits 1:0 – CMPMODE[1:0] Comparison Mode
Value | Name | Description |
---|---|---|
0 | LOW | When the converted data is lower than the low threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode. |
1 | HIGH | When the converted data is higher than the high threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode. |
2 | IN | When the converted data is in the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode. |
3 | OUT | When the converted data is out of the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode. |