38.6.1 ADC Control Register
This register can only be written if the WPCREN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMPRST | SWFIFO | START | SWRST | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
Bit 4 – CMPRST Comparison Restart
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Stops the conversion result storage until the next comparison match. |
Bit 3 – SWFIFO Software FIFO Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the internal FIFO, simulating a hardware reset. |
Bit 1 – START Start Conversion
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Begins analog-to-digital conversion. |
Bit 0 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the ADC, simulating a hardware reset. |