68.7.1 PWM Clock Register

This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the PWM Write Protection Status Register.

Name: PWM_CLK
Offset: 0x00
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
     PREB[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
 DIVB[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
     PREA[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 DIVA[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 27:24 – PREB[3:0] CLKB Source Clock Selection

ValueNameDescription
0 CLK

Peripheral clock

1 CLK_DIV2

Peripheral clock/2

2 CLK_DIV4

Peripheral clock/4

3 CLK_DIV8

Peripheral clock/8

4 CLK_DIV16

Peripheral clock/16

5 CLK_DIV32

Peripheral clock/32

6 CLK_DIV64

Peripheral clock/64

7 CLK_DIV128

Peripheral clock/128

8 CLK_DIV256

Peripheral clock/256

9 CLK_DIV512

Peripheral clock/512

10 CLK_DIV1024

Peripheral clock/1024

Other

Reserved

Bits 23:16 – DIVB[7:0] CLKB Divide Factor

ValueNameDescription
0 CLKB_POFF

CLKB clock is turned off

1 PREB

CLKB clock is clock selected by PREB

2–255 PREB_DIV

CLKB clock is clock selected by PREB divided by DIVB factor

Bits 11:8 – PREA[3:0] CLKA Source Clock Selection

ValueNameDescription
0 CLK

Peripheral clock

1 CLK_DIV2

Peripheral clock/2

2 CLK_DIV4

Peripheral clock/4

3 CLK_DIV8

Peripheral clock/8

4 CLK_DIV16

Peripheral clock/16

5 CLK_DIV32

Peripheral clock/32

6 CLK_DIV64

Peripheral clock/64

7 CLK_DIV128

Peripheral clock/128

8 CLK_DIV256

Peripheral clock/256

9 CLK_DIV512

Peripheral clock/512

10 CLK_DIV1024

Peripheral clock/1024

Other

Reserved

Bits 7:0 – DIVA[7:0] CLKA Divide Factor

ValueNameDescription
0 CLKA_POFF

CLKA clock is turned off

1 PREA

CLKA clock is clock selected by PREA

2–255 PREA_DIV

CLKA clock is clock selected by PREA divided by DIVA factor