68.7.13 PWM Sync Channels Update Period Update Register

This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels.

Name: PWM_SCUPUPD
Offset: 0x30
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     UPRUPD[3:0] 
Access WWWW 
Reset  

Bits 3:0 – UPRUPD[3:0] Update Period Update

Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register). This time is equal to UPR+1 periods of the synchronous channels.