68.7.14 PWM Interrupt Enable Register 2

This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.

Name: PWM_IER2
Offset: 0x34
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CMPU7CMPU6CMPU5CMPU4CMPU3CMPU2CMPU1CMPU0 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 CMPM7CMPM6CMPM5CMPM4CMPM3CMPM2CMPM1CMPM0 
Access WWWWWWWW 
Reset  
Bit 76543210 
     UNRE  WRDY 
Access WW 
Reset  

Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx Comparison x Update Interrupt Enable

Bits 8, 9, 10, 11, 12, 13, 14, 15 – CMPMx Comparison x Match Interrupt Enable

Bit 3 – UNRE Synchronous Channels Update Underrun Error Interrupt Enable

Bit 0 – WRDY Write Ready for Synchronous Channels Update Interrupt Enable