68.7.12 PWM Sync Channels Update Period Register

Name: PWM_SCUP
Offset: 0x2C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 UPRCNT[3:0]UPR[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:4 – UPRCNT[3:0] Update Period Counter

Reports the value of the update period counter.

Bits 3:0 – UPR[3:0] Update Period

Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register). This time is equal to UPR+1 periods of the synchronous channels.