68.7.35 PWM Write Protection Control Register
See Register Write Protection for the list of registers that can be write-protected.
| Name: | PWM_WPCR |
| Offset: | 0xE4 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WPKEY[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPKEY[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WPRG5 | WPRG4 | WPRG3 | WPRG2 | WPRG1 | WPRG0 | WPCMD[1:0] | |||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bits 31:8 – WPKEY[23:0] Write Protection Key
| Value | Name | Description |
|---|---|---|
| 0x50574D | PASSWD |
Writing any other value in this field aborts the write operation of the WPCMD field. Always reads as 0 |
Bits 2, 3, 4, 5, 6, 7 – WPRGx Write Protection Register Group x
| Value | Description |
|---|---|
| 0 | The WPCMD command has no effect on the register group x. |
| 1 | The WPCMD command is applied to the register group x. |
Bits 1:0 – WPCMD[1:0] Write Protection Command
This command is performed only if the WPKEY corresponds to 0x50574D (“PWM” in ASCII).
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE_SW_PROT | Disables the software write protection of the register groups of which the bit WPRGx is at ‘1’. |
| 1 | ENABLE_SW_PROT | Enables the software write protection of the register groups of which the bit WPRGx is at ‘1’. |
| 2 | ENABLE_HW_PROT | Enables the hardware write protection of the register groups of which the bit WPRGx is at ‘1’. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. |