68.7.38 PWM Comparison x Value Update Register

This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.

Only the first 16 bits (channel counter size) of field CVUPD are significant.

CAUTION: The write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx.
Name: PWM_CMPVUPDx
Offset: 0x0134 + x*0x10 [x=0..7]
Reset: 
Property: Write-only

Bit 3130292827262524 
        CVMUPD 
Access W 
Reset  
Bit 2322212019181716 
 CVUPD[23:16] 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 CVUPD[15:8] 
Access WWWWWWWW 
Reset  
Bit 76543210 
 CVUPD[7:0] 
Access WWWWWWWW 
Reset  

Bit 24 – CVMUPD Comparison x Value Mode Update

Note: This bit is not relevant if the counter of the channel 0 is left-aligned (CALG = 0 in PWM Channel Mode Register)
ValueDescription
0

The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.

1

The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

Bits 23:0 – CVUPD[23:0] Comparison x Value Update

Defines the comparison x value to be compared with the counter of the channel 0.