68.7.48 PWM Channel Dead Time Update Register

This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register.

This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the dead-time values.

Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant.

Name: PWM_DTUPDx
Offset: 0x021C + x*0x20 [x=0..3]
Reset: 
Property: Write-only

Bit 3130292827262524 
 DTLUPD[15:8] 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 DTLUPD[7:0] 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 DTHUPD[15:8] 
Access WWWWWWWW 
Reset  
Bit 76543210 
 DTHUPD[7:0] 
Access WWWWWWWW 
Reset  

Bits 31:16 – DTLUPD[15:0] Dead-Time Value Update for PWMLx Output

Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.

Bits 15:0 – DTHUPD[15:0] Dead-Time Value Update for PWMHx Output

Defines the dead-time value for PWMHx output. This value must be defined between 0 and the value (CPRD – CDTY) (PWM_CPRDx and PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.