68.7.51 PWM Leading-Edge Blanking Register
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
| Name: | PWM_LEBRx |
| Offset: | 0x0430 + (x-1)*0x20 [x=1..2] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PWMHREN | PWMHFEN | PWMLREN | PWMLFEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LEBDELAY[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 19 – PWMHREN PWMH Rising Edge Enable
| Value | Description |
|---|---|
| 0 |
Leading-edge blanking is disabled on PWMHx output rising edge. |
| 1 |
Leading-edge blanking is enabled on PWMHx output rising edge. |
Bit 18 – PWMHFEN PWMH Falling Edge Enable
| Value | Description |
|---|---|
| 0 |
Leading-edge blanking is disabled on PWMHx output falling edge. |
| 1 |
Leading-edge blanking is enabled on PWMHx output falling edge. |
Bit 17 – PWMLREN PWML Rising Edge Enable
| Value | Description |
|---|---|
| 0 |
Leading-edge blanking is disabled on PWMLx output rising edge. |
| 1 |
Leading-edge blanking is enabled on PWMLx output rising edge. |
Bit 16 – PWMLFEN PWML Falling Edge Enable
| Value | Description |
|---|---|
| 0 |
Leading-edge blanking is disabled on PWMLx output falling edge. |
| 1 |
Leading-edge blanking is enabled on PWMLx output falling edge. |
Bits 6:0 – LEBDELAY[6:0] Leading-Edge Blanking Delay for TRGINx
Leading-edge blanking duration for external trigger x input. The delay is calculated according to the following formula:
LEBDELAY = (fperipheral clock × Delay) + 1