68.7.7 PWM Interrupt Mask Register 1

Name: PWM_IMR1
Offset: 0x18
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     FCHID3FCHID2FCHID1FCHID0 
Access RRRR 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     CHID3CHID2CHID1CHID0 
Access RRRR 
Reset 0000 

Bits 16, 17, 18, 19 – FCHIDx Fault Protection Trigger on Channel x Interrupt Mask

Bits 0, 1, 2, 3 – CHIDx Counter Event on Channel x Interrupt Mask