68.7.40 PWM Comparison x Mode Update Register

This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x match.

Name: PWM_CMPMUPDx
Offset: 0x013C + x*0x10 [x=0..7]
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     CUPRUPD[3:0] 
Access WWWW 
Reset  
Bit 15141312111098 
     CPRUPD[3:0] 
Access WWWW 
Reset  
Bit 76543210 
 CTRUPD[3:0]   CENUPD 
Access WWWWW 
Reset  

Bits 19:16 – CUPRUPD[3:0] Comparison x Update Period Update

Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter.

Bits 11:8 – CPRUPD[3:0] Comparison x Period Update

CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter.

Bits 7:4 – CTRUPD[3:0] Comparison x Trigger Update

The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR.

Bit 0 – CENUPD Comparison x Enable Update

ValueDescription
0

The comparison x is disabled and can not match.

1

The comparison x is enabled and can match.