68.7.5 PWM Interrupt Enable Register 1

This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.

Name: PWM_IER1
Offset: 0x10
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     FCHID3FCHID2FCHID1FCHID0 
Access WWWW 
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     CHID3CHID2CHID1CHID0 
Access WWWW 
Reset  

Bits 16, 17, 18, 19 – FCHIDx Fault Protection Trigger on Channel x Interrupt Enable

Bits 0, 1, 2, 3 – CHIDx Counter Event on Channel x Interrupt Enable