68.7.9 PWM Sync Channels Mode Register

This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.

Name: PWM_SCM
Offset: 0x20
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 PTRCS[2:0]PTRM  UPDM[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     SYNC3SYNC2SYNC1SYNC0 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 23:21 – PTRCS[2:0]  DMA Controller Transfer Request Comparison Selection

Selection of the comparison used to set the flag WRDY and the corresponding DMA Controller transfer request.

Bit 20 – PTRM  DMA Controller Transfer Request Mode

UPDM

PTRM

WRDY Flag and DMA Controller Transfer Request
0 x The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are never set to ‘1’.
1 x The WRDY flag in PWM Interrupt Status Register 2 is set to ‘1’ as soon as the update period is elapsed, the DMA Controller transfer request is never set to ‘1’.
2 0 The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as soon as the update period is elapsed.
1 The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as soon as the selected comparison matches.

Bits 17:16 – UPDM[1:0] Synchronous Channels Update Mode

Note:
  1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in PWM Sync Channels Update Control Register is set.
  2. The update occurs when the Update Period is elapsed.
ValueNameDescription
0 MODE0

Manual write of double buffer registers and manual update of synchronous channels 1(1).

1 MODE1

Manual write of double buffer registers and automatic update of synchronous channels 2(2).

2 MODE2

The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as soon as the update period is elapsed.

Bits 0, 1, 2, 3 – SYNCx Synchronous Channel x

ValueDescription
0

Channel x is not a synchronous channel.

1

Channel x is a synchronous channel.